Office: 222 Cushing
University of Notre Dame: Dec 2015 (expected)
PhD Candidate – Computer Science and Engineering
Wayne State University: May 2011
Master of Science – Computer Science
Summary of Activities/Interests
My interests include all aspects of system/architecture/circuit design, modeling, testing, and power/performance analysis.
Languages: Verilog, SPICE, C/C++, Java, Python, Shell script
Software: MATLAB, Cadence, Simics, OOMMF
Graduate Research Assistant: Aug 2010 - present
University of Notre Dame Notre Dame, IN
- Designed a mixed signal architecture with FSM controller, for Cellular Neural Networks (CNNs) applications. Data paths designed to analytically approach cell dynamics. Power, delay measured via HSPICE (transistor-level simulation), large scale functional verification via Verilog AMS (RTL behavioral simulation).
- Developed analytical models for analog CNN's power and performance estimation.
- Designed CNNs based on emerging devices, e.g., Tunneling FETs (TFETs), Graphene transistors, SymFETs, for multi-valued image processing.
- Developed a systematic methodology for designing Nanomagnet Logic (NML) circuits.
- Served as Teaching Assistant for Computer Architecture course (Fall '10, Spring '12).
Graduate Research Assistant: Aug 2008 – Aug 2010
Wayne State University Detroit, MI
- Developed a parallel, data mining framework for AdaBoost and LogitBoost, that can learn efficient models in a distributed setting with significant speed-up.
- Developed a method for measuring dataset differences by learning constrained models.
Presidency University, Dept of ECE, Dhaka, Bangladesh: Aug 2006 – Aug 2008
State University of Bangladesh, Dept of CSE, Dhaka, Bangladesh: Jan 2005 – Aug 2006
Instructed: Computer Architecture, VLSI, Digital Logic Design, Digital System Design, Microprocessors, Digital Electronics
Travel award from IEEE International Conference, BIBM: Nov 2009
Thomas C. Rumble fellowship from Wayne State University: Aug 2008 – May 2009
- Indranil Palit, Qiuwen Lou, Nicholas Acampora, Joseph Nahas, Michael Niemier, and X. Sharon Hu, “Analytically Modeling Power and Performance of a CNN System”, to appear in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015.
- Behnam Sedighi, Indranil Palit, X. Sharon Hu, Joseph Nahas, and Michael Niemier, “A CNN-Inspired Mixed Signal Processor based on Tunnel Transistors”, in Design, Automation and Test in Europe (DATE), pp. 1150-1155, 2015.
- Qiuwen Lou, Indranil Palit, Andras Horvath, X. Sharon Hu, Michael Niemier, and Joseph Nahas, “TFET-based Operational Transconductance Amplifier Design for CNN Systems”, in Great Lakes Symposium on VLSI (GLSVLSI), pp. 277-282, 2015.
- Indranil Palit, Qiuwen Lou, Michael Niemier, Behnam Sedighi, Joseph Nahas, and X. Sharon Hu, “Cellular Neural Networks for Image Analysis using Steep Slope Devices,” in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 92-95, 2014.
- Indranil Palit, Behnam Sedighi, András Horváth, Xiaobo Sharon Hu, Joseph Nahas, and Michael T. Niemier, “Impact of steep-slope transistors on non-von Neumann architectures: CNN case study,” in Design, Automation and Test in Europe (DATE), pp. 1-6, 2014.
- András Horváth, Xiaobo Sharon Hu, Joseph Nahas, Michael T. Niemier, Indranil Palit, Robert Perricone, and Behnam Sedighi, “Architectural Impacts of Emerging Transistors,” in IEEE International New Circuits and Systems Conference (NEWCAS), pp. 69-72, 2014.
- Nandhini Chandramoorthy, Karthik Swaminathan, Matthew Cotter, Xueqing Li, Indranil Palit, Kevin Irick, Sharon Hu, Michael Niemier, and Vijaykrishnan Narayanan, “Understanding the Landscape of Accelerators for Vision,” in IEEE International Workshop on Signal Processing Systems (SIPS), pp. 280-285, 2014.
- Indranil Palit, Xiaobo Sharon Hu, Joseph Nahas, and Michael T. Niemier, “TFET based Cellular Neural Network Architectures,” in International Symposium on Low Power Electronics and Design (ISLPED), pp. 236-241, 2013.
- Indranil Palit, Xiaobo Sharon Hu, Joseph Nahas, and Michael T. Niemier, “Systematic Design of Nannomagnet Logic Circuits,” in Design, Automation and Test in Europe (DATE), pp. 1795-1800, 2013.