Wan Sik Hwang

1/04 ~ 7/07

National University of Singapore, Singapore

● Ph.D. in Department of Electrical and Computer Engineering. 

● Dissertation: Study of Advanced Gate Stack using High-K Dielectric and Metal Electrode.

3/01 ~ 2/03

Korea Aerospace University, Kyunggi-Do, Korea

● M.S. in Materials Engineering. 

3/94 ~ 2/01

Korea Aerospace University, Kyunggi-Do, Korea

● B.S. in Materials Engineering. 

9/95 ~ 2/98

Republic of Korea Air Force

● Military Service, Honorable Discharged as an airman first class

8/10 ~ Present

Research Assistant Professor: Midwest Institute of Nanoelectronics Discovery (MIND), University of Notre Dame, Notre Dame, IN

● Investigating Graphene Nano-Ribbon (GNR) tunneling field effect transistor which is funded by Semiconductor Research Corporation’s Nanoelectronics Research Initiative.

● Fabricated and characterized sub-10nm Graphene Nano-Ribbon in wafer size substrate, for the first time, showing a substantial bandgap and collaborating with Naval Research Laboratory (NRL) to improve the graphene transistors on SiC wafers.

● Developing a formation of graphene p-n junction by electrostatic, solid-electrolyte, and chemical bonding to the edges.

● Introducing ions (Li⁺ & ClO^-₄) graphene device for logic and memory applications.

● Correlating the experimental results with device modeling and developing the model for the tunneling FET using experimental results.

8/07 ~ 7/10

Senior Engineer: Process Development Team, Semiconductor R & D center, Samsung Electronics, Korea

● Developed the NAND Flash Memory for the 40 to 20nm node in the area of tunneling oxide, inter poly dielectric, floating gate, and control gate for floating memory as well as charge trap flash (CTF).

● Improved the performance of SONOS and TANOS gate stack using plasma and high-K dielectrics. (Requiring knowledge of operation physics and holding one Korea patent).

● Set up the pilot device process of vertical memory for sub 10nm node as a main leadership (Requiring an understanding of lithography, CMP, dry and wet etch, annealing, implantation, CVD, PVD, ALD deposition, low-K materials, device physics and holding 4 Korea patents).

● Involved the project of high-K inter poly dielectric (IPD) for floating gate and high-k blocking oxide for charge trap flash (CTF).

● Analyzed the interface trap between inter poly dielectric (IPD) for the floating gate memory devices and suggested the in-situ deposition of IPD.

● Identified the effect of plasma nitridation on the surface of floating gate and developed the selective removal of un-wanted plasma nitridation residue. (One Korea patent and one U.S patent is filed).   

● Set up Aixtron Atomic Layer Deposition (ALD) equipment and developed high-k dielectrics such as Al₂O₃, HfO₂, SiO₂, HfSiO, and AlSiO for memory and logic devices.

● Took responsibility for Atomic Layer Deposition (ALD) and Rapid Thermal Annealing (RTA) equipment.

1/04 ~ 7/07

Doctoral Research: Department of Electrical and Computer Engineering, National University of Singapore, Singapore

● Investigated formation of gate stack of metal electrode and high-K dielectrics.

● Examined various metal carbides such as HfC, TaC, WC, and VC for metal electrode and suggested HfC as a low work function electrode, resulting in presentation at VLSI 2007.

● Studied the hard mask effect during the metal electrode etching, leading to DPS 2005 Young Research Award.

● Examined the plasma etch residue effect on memory device using XPS and Certificated XPS super-user.

● Developed various high selectivity dry etching recipe for TaN, HfN,TiN, W, Ru, Pt, Ir, and poly-Si over HfO₂ gate dielectrics.

● Analyzed and developed the high selective etching of HfO₂ over Si substrate using low ion energy

● Took responsibility for plasma etcher, ashing, and PECVD equipment.

7/01 ~ 6/03

Assistant Researcher: MEMS division, Korea Electronics Technology Institute (KETI), Kyunggi-Do, Korea.

● Investigated LIGA (lithography, electroplating, and molding) process for MEMS